How to write constraint for generating a continuous mask

SystemVerilog
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7

In reply to ben@SystemVerilog.us:

You can use a function in a constraint as long as the random variable dependencies flow through correctly. For examlpe in the orginal example , you could write instead

constraint valid_mask{mask_validation(mask) -> b < 10; }

and that will always find a solution.

In reply to voraravi:
Yes, you’re correct the bit-width doesn’t matter in this case. I was worried that when N==8 the 'b1 would get truncated. But it turns out (9’b1_00000000 - 9’b0_00000001) and (8’b00000000 - 8’b00000001) both give me 'b11111111