How to write constraint for generating a continuous mask

SystemVerilog
,
4

In reply to Tapas:
Calling a user defined function in a constraint breaks the solution space in half. The inputs to the function get randomized to a solution first, then the function gets called, and the output of the function becomes a non-random state variable.In your example. if the output of mask_validation returns 0, it won’t go back and try another set of inputs until the output returns 1. the constraint will just fail.

What you need to do is express your constraints entirely as a set of equations.

class A;
  rand bit [7:0] mask;
  rand int unsigned N; // Number of ones
  rand int unsigned S; // shifted position
  constraint valid_mask {
    N inside {[1:8]};
    S <= 8-N;
    (9'b1 << N)-9'd1 << S == mask;
  }
endclass
module top;
  A a= new;
  initial repeat(100) begin
    assert(a.randomize());
    $display("mask %b N %0d S %0d",a.mask,a.N, a.S);
  end
endmodule