How to write a union data structure in systemverilog

SystemVerilog
2

In reply to zz8318:

“not yet supported” means your tool recognizes the construct, but has not implemented it yet. Also, SystemVerilog does not have struct bit-fields.

What you want is a packed struct, not a union.

typedef struct packed {
 bit [24:0] offset;
 bit [6:0] id;
} my_dw;

my_dw data;

Then you can refer to data, or data.id, data.offset. (data by itself would be the whole thing)