How to write a assertion to check a 2D array that all its elements with the value zero

SystemVerilog
1

Can we use SVA to write a assertion to check that a two dimensional array is all zero?

2

Can we use SVA to write a assertion to check that a two dimensional array is all zero?

Use a function call.

function bit f_2D(type twod); // pseudocode 
    ...
   if(...) return 1; 
   else return 0;
endfunction 

property p_option1; 
    bit v; 
   (@ (posedge clk)  cond |-> (1, v=f_2D(my_array) ##0 v; 
endproperty
// Note, you may also use the function directly: 
ap_option2: assert property(@ (posedge clk)
       cond |->  f_2D(my_array)  );