In reply to srikanth_manukonda:
I am verifying clock gate, which has clk_in, clk_en and clk_out.
How to write a logic which verifies : clock is not generated when input clock is present and clock is enabled.
How about assertions instead. Here I used a delayed version of the clk in the assertions to get away from glitches and use sampling regions that are stable. The clk_out is delayed from clk because of the gating.
import uvm_pkg::*; `include "uvm_macros.svh"
module m;
bit clk, clk_dly, enb, clk_enb, clk_out;
initial forever #10 clk=!clk;
ap_pos_enb1: assert property(@(posedge clk_dly) clk_enb |-> clk_out==1'b1 );
ap_neg_enb1: assert property(@(negedge clk_dly) clk_enb |-> clk_out==1'b0 );
ap_pos_enb0: assert property(@(posedge clk_dly) !clk_enb |-> clk_out==1'b0 );
ap_neg_enb0: assert property(@(negedge clk_dly) !clk_enb |-> clk_out==1'b0 );
always @(posedge clk) begin
if(enb) clk_enb <= 1'b1;
else clk_enb <=1'b0;
end
assign #1 clk_dly=clk;
assign clk_out = (clk_enb) ? clk : 1'b0;
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(enb) with
{ enb dist {1'b1:=1, 1'b0:=3};
}) `uvm_error("MYERR", "This is a randomize error")
end
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115