In reply to saritr:
If by signal, you mean an RTL variable or net, the answer is not directly. There are no pointers in SystemVerilog. You can only get handles to class objects and interface instances.
In reply to saritr:
If by signal, you mean an RTL variable or net, the answer is not directly. There are no pointers in SystemVerilog. You can only get handles to class objects and interface instances.