In reply to ANASHKU:
I think you are confusing UVM factory class overrides with how SystemVerilog class inheritance works with method overrides. Both factory overrides are happening to the 2 separate components you created. But each class override only overrides one of the methods.
If you would have extended component_C from component_B, then you would have gotten the “inside display component_B” from component_C.
What you seem to be looking for might be what is known as a policy class. This is where you can associate each method with a seperate class, and override them individually, See Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 – DVCon Proceedings Archive