How to use first_match in assertion

SystemVerilog
, ,
5

I Understood the concept of first_match , But my question why if I replace overlapping operator with non-overlapping antecedent triggers many time.

i am writing assertion for this condition

module reset_check(input bit[31:0] datain);
bit temp_clk;
bit clk;
bit reset;
always temp_clk = #5ns ~templ_clk;
assign clk = (set_clk)?temp_clk:0;


initial begin
reset =1'b1;
set_clk =1'b0;
#20ns;
reset= 1'b0;
#30ns;
set_clk =1'b1;
// Some Other code

end

default clocking utmi_clk @(posedge clk) endclocking;
 
 property pro_check_after_reset;
// If i use this condition assertion runs only one time
        first_match(reset==0) |-> (datain ==0);
// If i use this condition assertion runs many time
  first_match(reset==0) |=> (datain ==0);

 endproperty


assert property(pro_check_after_reset);
endmodule