In reply to cashah85:
SystemVerilog has arrays of arrays, not really multidimensional arrays. You need to check the dimensions one by one. You can do this with an if-tree, or use the short-circuit expression guards to prevent accessing non-existant elements.
module top;
int aa[int][int];
initial begin
$display(aa.exists(1) && aa[1].exists(2 )); // 0
aa[1][2] = 3;
$display(aa.exists(1) && aa[1].exists(2 )); // 1
aa[3][4] = 5;
$display(aa.exists(3) && aa[3].exists(3 )); // 0
$display(aa.exists(3) && aa[3].exists(4 )); // 1
end
endmodule