How to use class variables inside an assertion module?

SystemVerilog
,
8

In reply to rajan passionate:

Can you post the error message. I believe the cfg in assertion is pointing to null at time 0.

Try replacing always block with initial block with forever and add a statement wait(cfg != null).

initial
begin
  wait(cfg != null);
  forever
  begin
    @(posedge clk);
    . . .
    data_tran_RD    = cfg.data_tran_RD;
    data_tran_WR    = cfg.data_tran_WR;
    slave_addr_tran = cfg.slave_addr_tran;
    . . .
  end
end

Try this and let me know if it worked…