How to understand the run_phase in the uvm test

In reply to zz8318:

In reply to chris_le:
I’ll try to do that referring to your 1st suggestion . Thank you .
May I know how to understand your 2nd suggestion ? It is correct or not if I have forever loop in the run_phase of the components ?

If you have a forever loop that doesn’t consume time (zero time statements), your simulation will hang at that loop. This is very popular issue.

But a forever loop that consumes time such as your driver component is ok (your driver will be blocked at get_next_item and finish when all objection are dropped in run_phases of all other components).