How to turn off Assertions?

UVM
3

This is not working, I am getting an error.

import uvm_pkg::*;
`include "uvm_macros.svh"

 class tb_env extends uvm_component;
  `uvm_component_utils(tb_env)

  int exp_val = 0;
  int act_val = 0;

  function new(string name = "tb_env", uvm_component parent = null);
    super.new(name, parent);
  endfunction

  virtual task run_phase (uvm_phase phase);
    super.run_phase(phase);
    phase.raise_objection(this);
    #10;
    ASRT: assert ( exp_val == act_val) else
     `uvm_error(get_full_name(), "Error");
    
    ASRT1: assert ( exp_val == act_val) else
      `uvm_error(get_full_name(), "second assertion Error");
    
    #10;
    `uvm_info(get_full_name(), "Done Env", UVM_LOW);
    phase.drop_objection(this);
  endtask : run_phase
endclass

 

module tb_run;
  //tb_env env = new();
  
  initial
  begin
      tb_env env = new();

    //$assertoff(0,env.run_phase.ASRT);  
    //$assertoff(0,env.run_phase.ASRT1);
    
       //$assertoff(0);
       $assertoff(0,env);

     fork
       run_test();
       begin
         #5;
         env.exp_val = 1;
         $display("@%0t : exp_val - %0b, act_val - %0b", $time(), env.exp_val, env.act_val);
       end
     join
  end
endmodule

Error-[WRONGARGCNTRLTASK] Illegal argument of control task
testbench.sv, 43
“$assertoff(0, env);”
Argument of SVA control task should be module, hierarchical instance or
assertion