How to slice an array with start and end values are passed from other function

SystemVerilog
1

Hi

I have been trying to slice an array with two variable start and end and assign it to a variable . Please find the below code

data_ca = cach[index_req][start:end]; //start and end are global variable set in different function and are calculated first.

The issue comes during compilation as it cant predict the sizes and keep saying illegal range assignment. Any help on how to resolve this issue .

2

The overall composition of SystemVerilog requires that all slices/ranges have constant sizes/widths. If Start and End were defined as parameters, not variables, this would work. Note that you can define the value of a parameter with a function as long it meets certain requirements (See section 13.4.3 Constant functions in the 1800-2017 LRM)

To get your desired functionality you can either use for loops, or the streaming operator {>>{}}. The streaming operators has a feature that allows slicing of variable sized unpacked arrays. See section 11.4.14.4 Streaming dynamically sized data.

module top; 
  bit [7:0] cach[2][10],data_ca[];
  int index_req,Start,End; // end is a reserved keyword
  
  initial begin
    cach[0] = {1,2,3,4,5,6,7,8,9,10};
    Start=2;End=5;
    data_ca = {>>{cach[index_req] with [Start:End]}}; 
    $display("%p",data_ca);
  end
endmodule
3

Thanks, Dave