How to setup a backdoor access within UVM RAL model?

UVM
,
3

In reply to cgales:

THANK YOU really. cgales.

To check Backdoor access, I added UVM_INFO as the below,

    `uvm_info(get_type_name(), "BACKDOOR ACCESS START", UVM_LOW);
    reg_model.mod_reg.control_reg.write(status, 32'h9876_5432, UVM_BACKDOOR, .parent(this));
    reg_model.mod_reg.control_reg.read(status, read_data, UVM_BACKDOOR, .parent(this));
    `uvm_info(get_type_name(), "BACKDOOR ACCESS FINISH", UVM_LOW);

But this BACKDOOR ACCESS doesn’t work. it seems like to skip.
There is no any message inside START to FINISH.

# UVM_INFO base_seq.sv(35) @ 14: uvm_test_top.env_o.agt.seqr@@rseq [reg_seq] BACKDOOR ACCESS START
# UVM_INFO base_seq.sv(38) @ 14: uvm_test_top.env_o.agt.seqr@@rseq [reg_seq] BACKDOOR ACCESS FINISH

What am I supposed to do to resolve skip problem?
I linked to RAL example(3) - EDA Playground