I have defined a macro in my define file, for example-
ifndef ABC define ABC 5
`endif
So if I will not define ABC from command line then it will use value 5 obviously which I have defined in define file.
But if I want to set a new value of ABC (let’s say 3) from command line. So I used command “make -f Makefile +define+ABC=3”.
But still I am getting value 5 of ABC.
What am I doing wrong here? Please correct me.
In reply to kumarmohit.ec:
The ‘make’ command parses your Makefile, which will then in turn call your SystemVerilog compiler. You need to look at your Makefile and understand how the defines on you call to ‘make’ get passed to your SystemVerilog compiler. A Makefile uses a different format for defining variables.
I have a similar issue as kumarmohit has. How can I override the value of the define ABC to 3 from the command line?
In reply to VarshaAnand2402:
There is no switch of the uvm cmd line processor for the defines. But you can do this using your own, application-specific macro-file or using the the setting of the toool-specific define setting.
In reply to kumarmohit.ec:
when you give this command make -f Makefile +define+ABC=3, command-line argument will be passed to the makefiles parameter. so now from Makefile you need again pass this argument.
like your Makefile should have some code that takes command-line arguments and that will be passed to tool-specific command like vsim. Hope you get my point.