In reply to chr_sue:
hi Chr_sue,
im getting this error when im connecting in agent analysis port to analysis export connections. “0:E:m_sequencer.res_fifo: Connection Error: connection count of 0 does not meet required minimum of 1”. please find the below code
class interrupt_agent extends vvm_agent_c;
// Factory Registration
`uvm_component_utils(interrupt_agent)
// Declare handles of interrupt_monitor,iterrupt_sequencer
interrupt_mon monh;
interrupt_sequencer m_sequencer;
virtual mcu_status_if intr_vif;
//------------------------------------------
// METHODS
//------------------------------------------
// Standard UVM Methods:
extern function new(string name = “interrupt_agent”, uvm_component parent = null);
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);
endclass : interrupt_agent
//----------------- constructor new method -------------------//
function interrupt_agent::new(string name = “interrupt_agent”, uvm_component parent = null);
super.new(name, parent);
endfunction
//----------------- build() phase method -------------------//
// Call parent build phase
// Create interrupt_agent instance
// If is_active=UVM_ACTIVE, create interrupt_agent and interrupt_agent instances
function void interrupt_agent::build_phase(uvm_phase phase);
super.build_phase(phase);
m_sequencer=interrupt_sequencer::type_id::create(“m_sequencer”,this);
monh=interrupt_mon::type_id::create("monh",this);
`
endfunction
//----------------- connect() phase method -------------------//
//If is_active=UVM_ACTIVE,
//connect driver(TLM seq_item_port) and sequencer(TLM seq_item_export)
function void interrupt_agent::connect_phase(uvm_phase phase);
super.connect_phase(phase);
monh.intr_vif = intr_vif;
monh.ap.connect(m_sequencer.res_fifo);
endfunction
////////////////////////////Sequencer///////////////////
class interrupt_sequencer extends vvm_sqr_c #(interrupt_transaction);
`uvm_component_utils(interrupt_sequencer)
//uvm_tlm_analysis_fifo#(interrupt_transaction) res_fifo; //I have used both tlm analysis fifo and analysis_export
uvm_analysis_export #(interrupt_transaction) res_fifo;
function new(string name=“interrupt_sequencer”,uvm_component parent=null);
super.new(name);
res_fifo = new(“res_fifo”,this);
endfunction
endclass
/////////////////Monitor/////////////////
class interrupt_mon extends vvm_monitor_c;
//////////////////////factory registration/////////////////////
`uvm_component_utils(interrupt_mon)
//uvm_blocking_peek_imp#(interrupt_transation) intr_imp;
//////////////////////virtual interface //////////////////////
virtual mcu_status_if intr_vif;
interrupt_transaction intr_txn;
uvm_analysis_port #(interrupt_transaction) ap;
function new(string name=“interrupt_mon”, uvm_component parent);
super.new(name, parent);
ap = new(“ap”,this);
endfunction : new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
intr_txn = interrupt_transaction::type_id::create(“intr_txn”);
endfunction : build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
endfunction : connect_phase
task run_phase(uvm_phase phase);
forever begin
@(posedge intr_vif.McuClk);
intr_txn.interrupt = intr_vif.Interrupt;
`
ap.write(intr_txn);
end
endtask : run_phase
function void report_phase(uvm_phase phase);
`uvm_info(get_type_name(), “Interrupt Entering into Monitor”, UVM_LOW)
endfunction
endclass