In reply to sharvil111:
Thanks a lot sharvil111 and Dave for the answers. I will have to modify the compilation settings then.
Just to clarify the context in which I’d like to replace modules in the DUT. When designing sensors the input to your DUT is not an actual port, but some kind of energy (eg. light, noise, vibration) that is converted into quantities within the DUT. Normally when simulating your system you need a model (probably written in Verilog-AMS) which performs this conversion from some kind of input (eg. input file).
When designing a SV testbench you want to take advantage of SV constructs to model your conversion instead of relying on the legacy model that is instantiated within the DUT, but still keeping the option to choose between them (legacy and SV).