In reply to chr_sue:
In reply to ce_2015:
Your error message might depend on oher cntent in your VHDL pckage. Only types cn be shared between VHDL and SV.
And that is possible, and unfortunately I can’t do anything about the other content. Returning to the original problem and that is getting a hierarchical reference into the VHDL into the UVM Component (Scoreboard). At the very least I have been able to get everything to compile when I suppress the 7053 error (the one that doesn’t allow hierarchical references from packages).
I would prefer a better solution though if possible to giving the Scoreboard access to the regmap…