In reply to ldm_as:
There’s no way to read a string name and find a matching variable name with SystemVerilog. There are solutions using the VPI (C interface to the simulator) and tool specific mechanisms, but those will all have poor performance implications.
A better solutions might be to convert your text file to a file with executable SystemVerilog syntax.
If the variables names are fixed and you just need to read the data. then you can use $fscanf to read the data into intermediate variables and cast them to the actual needed variables.