How to randomize a int variable with 2 mandatory values?

SystemVerilog
4

In reply to Prat_0693:

Here is a version to use randc cyclic random constraint.


import uvm_pkg::*; 
`include "uvm_macros.svh" 

`define aint 4
`define amax 10

class my_class extends uvm_object;
 
  randc int a; 
  constraint a_range {a inside {0,`amax, `amax+1, `amax+2};}

  rand int unsigned c, d; 
  constraint c_d_range { c inside {[1:`amax-1]};
                         d inside {[1:`amax-1]};
                       }
  
  
  function void post_randomize();
    case(a)
      `amax+1: a = c;
      `amax+2: a = d;
      default: begin end //Do nothting
    endcase
  endfunction  
  
endclass

module tb ();
  
  my_class my_obj;

  initial begin
    my_obj = new();
    for(int i=0; i< `aint*4; i++) begin
      void'(my_obj.randomize());
      $display("a%0d = %-0d", i%`aint, my_obj.a);
    end
  end
  
endmodule

simulation result as below:
a0 = 10
a1 = 0
a2 = 8
a3 = 6

a0 = 10
a1 = 9
a2 = 5
a3 = 0

a0 = 6
a1 = 10
a2 = 0
a3 = 5

a0 = 4
a1 = 10
a2 = 0
a3 = 7