How to pass delay through a variable in assertion

SystemVerilog
4

Hi,

The below code worked:

property prop;
int w_delay;
@(posedge clk)
((w_trig && req==1), w_delay= delay+1’b1) |-> (w_delay>0, w_delay=w_delay-1’b1, display("w_delay=%0d",w_delay))[*0:] ##0 w_delay==0 ##0 (ack == 1);
endproperty

P1: assert property(prop) $info(“KING Assertion pass”);
else $error(“KING Assertion fail”);

Regards,
Dilip