How to pass delay through a variable in assertion

SystemVerilog
2

In reply to myselfprakhar:

hey prakhar,
try this one


property @(posedge clk)
  int w_delay;
  ((w_trig && req==1), w_delay= delay+1'b1) |-> (w_delay>0, w_delay=w_delay-1'b1)[*0:$] ##0 w_delay==0 ##0 (ack == 64);

endproperty