How to make different binds of the same assertion module?

SystemVerilog
2

In reply to Raj Guru:

There are several variations of the bind statement that allows you to target specific instances of a module instantiation:

To instantiate instantiated_module in all instances of target_module:
bind target_module instantiated_module instantiation_name(port_connections);

To instantiate instantiated_module in all instances of target_module with instance name of a1:
bind target_module:a1 instantiated_module instantiation_name(port_connections);

To instantiate instantiated_module in a hierarchical instance of target_module:
bind target_module:dut.sub_block.a1 instantiated_module instantiation_name(port_connections);

You likely want to use the third variation.