Currently we are using run_phase. We start to see issue when we want to replace run_phase with multiple run-time phases.
It is a bit tricky because two sequence/sequencer pairs are involved and one sequence acts as a RAL proxy. It runs into a deadlock condition where one sequence (RAL access) is trying to do a write (through uvm_reg_map’s do_write) to keep pushing more sequence item to reg_seqr but the other sequence stops fetching request.
In reply to chr_sue: