wangdongya,
As Ben suggests, if you mean how the simulator conceptually models the timing of a circuit, I highly recommend what he does - trying to understand the event scheduling regions. See his diagram or (http://systemverilog.us/vf/Timing_flow.pdf) or the SystemVerilog 2017 LRM, Figure 4-1.
Understanding what happens in a time slot will provide a solid base knowledge, I think.
Ben, in your Timing_flow.pdf diagram/page, I think “Execution of events in the queue may re-trigger an earlier time slot.”, should be
“Execution of events in the queue may re-trigger an earlier event region.”
I only bring this up here, because of some confusion I ran into with the terminology of ‘time slots’, ‘time steps’, and other terms in describing event scheduling, as I asked here: