In reply to drorb:
SystemVerilog packages are global definitions; you cannot override the them.
You can set up the IP to use a package as default parameter types and values, and then when you instantiate the IP, you can override them on a per instance basis.
package global;
typedef int Word_t;
parameter int SIZE = 123;
endpackage
module IP();
import global::*;
parameter int SIZE = global::SIZE;
Word_t array[SIZE];
endmodule
The parameter SIZE declaration in IP prevents importing global::SIZE. Now when you instantiate IP, you can override SIZE. I’m assuming you only need to override values, but you can use the same mechanism with parameter types.