In reply to NaveenReddy:
For Q1, I think you have the correct understanding. Both streaming operator and cast define a intermediate linear “bitstream” of data the goes between the source and destination. If SystemVerilog defines a way for a source variable of a particular type into that bitstream, then there’s a way to get to the target using the reverse definition.
For Q2, first i hope you’re not confusing static cast with static variable lifetimes. Declaring static variables in not necessary for discussing bitstreams. I don’t see a problem with your method 1. You just have to make sure that all elements are covered, or use a default. Your function initArr is returning a 3-dimensional array and you are trying to assign it to 2-dimensions of my_arr. I don’t understand what your overall goal is.