How to implement RAL for multiple register banks with common address differentiated by the Interface level ports

UVM
4

The way you’d do it is to define a register block for the module registers:


class module_reg_block extends uvm_reg_block;
  some_reg_type SOME_REG;
endclass

In your system, you since the module is instantiated 4 times you’ll need 4 instances of the register block:


class system_reg_block extends uvm_reg_block;
  module_reg_block module_regs[4];

  // ...

  virtual function void build();
    for (int i = 0; i < 4; i++) begin
      module_regs[i] = module_reg_block::type_id::create("...");
      module_regs[i].build();
      module_regs[i].map(default_map, i * offset);
    end
  endfunction
endclass

The ‘i * offset’ factor allows you to control where the specific register block gets mapped. Indirectly this will affect where each instance of the containing regs gets mapped.