How to get virtual interface in sequence

UVM
28

In reply to chr_sue:

I think we are talking about the same thing.
https://verificationacademy.com/cookbook/sequences/layering

I agree, there is no time dependency. I’m just saying that interactions with the DUT that don’t have any association to the interface in question should not be handled by that agent. I.e. I shouldnt be putting fields into my UDP packet transaction like “bit wait_on_init”. It doesn’t know anything about that, nor should it. Putting a delay in, sure thats perfectly normal.

Sure, I can use the RAL to access a register, but I would have to poll it. That means I need a delay. How would you delay here (using TLM)? I’m guessing that answer is to create a “system” transaction, and start that on a “system” agent, where the interface will expend clock cycles. you agree?

// sequence
virtual task body();

  while (data==0) begin
    <------ need to delay here
    dut_ral.ctrl_reg.read(.status(status), .value(data), .parent(this));
  end

endtask