How to get type name on systemVerilog

SystemVerilog
,
2

In reply to uvm_share:

You can use VPI to get the name of the module or interface.
Here is an example you can use and works on questa:

test.sv:

interface if1();
endinterface
interface if2();
endinterface

module top;
import "DPI-C" context task get_if_name(string scope);
  if1 master();
  if2 slave();
  initial begin
    get_if_name("top.master");
    get_if_name("top.slave");
  end
endmodule

test.c:

#include <sv_vpi_user.h>
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
extern int get_if_name(char *scope);
int get_if_name(char *scope) {
  vpiHandle h = vpi_handle_by_name(scope, NULL);
  if(h) {
    printf("If Name for %s is: %s\n", scope, vpi_get_str(vpiDefName, h));
  }
  return 0;
}

Compile and run Makefile:

all: test.so
gcc -c -fPIC -I{QUESTA_SIMULATOR_HOME}/include test.c -o test.o
gcc -fPIC -shared test.o -o test.so
vlog -64 test.sv
vopt -64 top +acc -o top_opt
vsim -64 -c -do “run -all; quit -f” top_opt -sv_lib test

Output:

If Name for top.master is: if1

If Name for top.slave is: if2