In reply to chr_sue:
In reply to ramDV:
I believ you are pasting the wrong code, because the code below runs in my environment and I do not see problems with the enumeration type:
package eda_e1;
//`include "uvm_macros.svh"
typedef enum {A,B,C}adr_e;
class example;
rand adr_e adr;
rand bit talk;
endclass
endpackage
import uvm_pkg::*;
`include "uvm_macros.svh"
//import eda_e1::*;
module tb;
import eda_e1::*;
example ex1;
bit clk;
bit s1,s2;
/////////////This is my requeremnt to get the class enum varibale in the module/////////////
/*
property p1();
@(posedge clk) disbale iff(ex1.adr==A)
s1 |-> ##4 s2;
endproperty
C1: assert property (p1);
*/
initial begin
s1=1'b1;
#20;
s2=1'b1;
end
initial begin
clk=1'b0;
#5 clk=~clk;
end
initial begin
ex1=new();
end
endmodule
i need write assertion for the particular bit is high in transaction random packet based on this my assertion should work