i have to generate my clock from the driver instead of top module.can we use interface signal as it is whil;e generating the clock.
task gen;
bit testclk = 0;
if (testmode_en ==1)
Fork
While (1)
Begin
#20 test_clk = ~test_clk;
stc_IF.Testmode_clk <= test_clk;
end
join_any
end
endtask:gen
this code i have written in the driver…but clock is not generating .plz help me.
You have not shown nearly enough code for anyone to help you. Do you know if the while loop is even being executed?
This style of clock generation is very poor for performance. The clock signal is usually the most active signal in a simulation and you want the least amount of indirection. A much better suggestion is to put this looping task inside the interface and have the driver call the task.
Could you please explain a bit more on how is it different to have the clocks generated inside the interface tasks than the driver tasks?
Thanks in advance!
Dave,
Thanks a lot for your response. So, from the simulation performance point of view, the way inside_clk getting generated will have better performance compared to outside_clk and is recommended? Is my understanding correct?