How to generate a random number of two different ranges

SystemVerilog
2

In reply to murali.gubba:

class myclass
  rand bit [31:0] number;
  constraint ranges { 
     number inside { [32'h0200_0000:32'h0200_8FFF], 
                     [32'h4000_2000:32'h4000_3FFF]}; }
endclass

I assume your last number was a typo.