How to force/deposit string path in system verilog?

SystemVerilog
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5

In reply to dave_59:

Hi Dave,

Thanks for the response.
Actually, I have tried to create macro to covert integral type(instance path) into string and somehow i achieved it. Please see the snippet of the code.

   string hpath;
   `define STRINGIFY(x) $sformatf("%0s", `"x`")
   
   `define DO_FORCE(HPATH, val)\
     `ifdef SV\
        force HPATH = ``val;\
     `elsif UVM\
        hpath = `STRINGIFY(HPATH);\
        $display("%0s", hpath); \
        if(!uvm_hdl_check_path(hpath))\
          $error("ABCD :: %s path not found", hpath);\
        uvm_hdl_force(hpath, ``val);\
     `endif\

     `DO_FORCE(top.chip.block,10);

Is this approach is okay to use? can you feel any issue with this? Please suggest.
Please note that, define SV/UVM is defined based on environment type. (Eg, +define+SV or +define+UVM). Here, i want to make common support, which can be use by SV or UVM environment.

Thanks and Regards,
Mitesh Patel