How to drive Interface Signals to DUT?

In reply to rag123:

There are a few questions:
(1) what is the meaning of clk in your seq_item?
(2) Is your driver clock independent? If this would work you are stucking at time 0
(3) You do not pass the virtual interface to your driver. Instead you are trying to use a hierarchical path which does not exist.

Look into the cookbook to find more details:
https://verificationacademy.com/cookbook/uvm