How to define a condition for a covergroup (using iff)?

SystemVerilog
8

In reply to dave_59:

I tried two different ways like below, but both ways give me syntax error in compilation. Can you please help?

`define ABC\
    if (type_a == XYZ)
    	bins out_bound[] = {[10:18],[37:45]};
    if (type_a == PQR)
    	bins ou_bound[] = {5,[10:18],25,[37:45]};


`define DEF\
	bins out_bound[] = {[10:18],[37:45]} iff (type_a == XYZ) or {5,[10:18],25,[37:45]} iff (type_a == PQR);