How to debug a bidirectional port?

SystemVerilog
,
3

In reply to Verif Engg:

If I have a port on the DUT that is ‘inout’ how do I debug the activity on this port? How do I tell which component is driving which value?

Another approach that is tool independent is to use the $onehot0() method.
Here, you write an assertion (concurrent or immediate) that tests that all tri-state drives are one hot or are all in the OFF state. Below is an example:


import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
	logic clk=0, s1, s2, b, c; 
	wire w1, w2; 
	assign w1 = s1 ? b : 'Z;
	assign w2 = s2 ? c : 'Z; 

	initial forever #10 clk=!clk;  

	initial begin 
		repeat(200) begin 
			@(posedge clk);   #2; 
			a_1hot: assert ($onehot0( {s1, s2} )); // <-- THE DEBUG Assertion
			if (!randomize(s1, s2, b, c)  with 
					{ s1 dist {1'b1:=1, 1'b0:=4};
					  s2 dist {1'b1:=1, 1'b0:=3};
					  b dist {1'b1:=1, 1'b0:=2};
	                  c dist {1'b1:=1, 1'b0:=2};
					}) `uvm_error("MYERR", "This is a randomize error")
		end 
		$stop; 
	end 
endmodule

Ben Cohen
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