How to create the queue array of class from text file

UVM
17

In reply to rupeshblr:

Please see here. Consider this code as a template.

class my_seq_item extends uvm_sequence_item;
  rand int addr;
  rand logic [63:0]  data;
  rand int   delay;
  rand int   len;
  rand int   opc;
  rand int   mid;

  `uvm_object_utils(my_seq_item)

  function new(string name="my_seq_item");
    super.new(name);
  endfunction

endclass

class svci_master_reg_seq extends svci_master_seq;

int addr_qu[$];                   // address queue
logic [63:0]  expect_mem [int];   // associative array
 
  function new(string name="svci_master_reg_seq");
    super.new(name);
  endfunction
 
  `uvm_object_utils(svci_master_reg_seq)
 // `uvm_declare_p_sequencer(svci_master_sequencer)   // p_sequencer is not a really good idea
 
 
  virtual task body();

     bit [63:0] data;
     my_seq_item item;
     item = my_seq_item::type_id::create("item");

     // fill the addr_queue;
     for (int i = 0; i < no_of_regs; i++)
       addr_queue.push_back(<reg_addresses>);
     addr_queue.shuffle();    // randomize the addresses  

     // Writing all regs
     foreach (addr_queue[i]) begin
       void'(item.randomize() with {addr == addr_queue[i]; delay == 8; len == 2; opc == 2; mid == 2;});
       svci_master_write(.addr(item.addr), .data(item.data), .delay(item.delay), .len(item.len), .opc(item.opc), .mid(item.mid));
       `uvm_info(get_type_name(), $sformatf("writing req addr = %0d with data = %0h ", addr_queue[i], data), UVM_MEDIUM)
       expect_mem[addr_queue[i]] = item.data;
     end   

    // Reading all regs
     addr_queue.shuffle();    // randomize the addresses  
     foreach (addr_queue[i]) begin
       svci_master_read(.addr(addr_queue[i]), .data(data), .delay(`h8), .len(`h2), .opc(`h2), .mid(`h2));
       if (data == expect_mem[addr_queue[i]])
	 `uvm_info(get_type_name(), $sformatf("check passed for addr = %0d", addr_queue[i]), UVM_MEDIUM)  
       else	 
	 `uvm_error(get_type_name(), $sformatf("check failed for addr = %0d", addr_queue[i])
     end	 
 
<<<<<list of all registers>>>>>>>>>>>>>>>
 
  endtask
 
endclass : svci_master_reg_seq