How to create the queue array of class from text file

UVM
14

In reply to chr_sue:

class svci_master_seq extends svci_base_sequence;

  //Sequence instantiation 
  master_write_cmd_seq	write_seq;
  master_read_cmd_seq	read_seq;
  svci_master_id_pkt	master_id_pkt;
  //int			valid_tag_q[$];
  int		 	j,seq_error_set,valid_tag_q[0:((2**`SVCI_TAG_ID_WIDTH)-1)];

  function new(string name="svci_master_seq");
    super.new(name);
  endfunction

  `uvm_object_utils(svci_master_seq)
  

  virtual task body();
  endtask

  task svci_master_write(bit [31:0] tag='hDEAD,bit [31:0] mid='hDEAD,bit [31:0] addr='hDEAD,
                                 bit [63:0] data='hDEAD,bit [31:0] len='hDEAD,cmd_opc_t opc='hDEAD,
                                 bit [31:0] prty='hDEAD,bit [31:0] delay='hDEAD);

     << Logic >>>
  endtask

  task svci_master_read(bit [31:0] tag='hDEAD,bit [31:0] mid='hDEAD,bit [31:0] addr='hDEAD,bit [31:0] len='hDEAD,cmd_opc_t opc='hDEAD,bit [31:0] prty='hDEAD,bit [31:0] delay='hDEAD);
<<<<logic>>>>>>>>>>>>.     

  endtask

 
endclass : svci_master_seq

class svci_master_reg_seq extends svci_master_seq;

  function new(string name="svci_master_reg_seq");
    super.new(name);
  endfunction

  `uvm_object_utils(svci_master_reg_seq)
  `uvm_declare_p_sequencer(svci_master_sequencer)


  virtual task body();
   reg [63:0] data ;
      for (int i= 0 ; i<= 4; i++)
       begin
         if (i == 0)
         data = 64'hffffffffffffffff;
         else if (i == 1)
         data = 64'hAAAAAAAAAAAAAAAA;
         else if (i == 2)
         data = 64'h5555555555555555;
         else 
         data = 64'h0000000000000000;
  $display ("svci_reg_addr = %h ",`VERSION_ID +`REG_OFFSET );
    svci_master_write(.addr(`VERSION_ID +`REG_OFFSET ), .data(data), .delay('h8), .len('h2), .opc('h2), .mid('h2));
    svci_master_read(.addr(`VERSION_ID +`REG_OFFSET ),  .delay('h8), .len('h2), .opc('h0), .mid('h2));

    $display ("svci_reg_addr = %h ",`IP_FORCE_CG +`REG_OFFSET );
    svci_master_write(.addr(`IP_FORCE_CG +`REG_OFFSET ), .data(data), .delay('h8), .len('h2), .opc('h2), .mid('h2));
    svci_master_read(.addr(`IP_FORCE_CG +`REG_OFFSET ),  .delay('h8), .len('h2), .opc('h0), .mid('h2));

    $display ("svci_reg_addr = %h ",`IP_CG_STATUS +`REG_OFFSET );
    svci_master_write(.addr(`IP_CG_STATUS +`REG_OFFSET ), .data(data), .delay('h8), .len('h2), .opc('h2), .mid('h2));
    svci_master_read(.addr(`IP_CG_STATUS +`REG_OFFSET ),  .delay('h8), .len('h2), .opc('h0), .mid('h2));

  
<<<<<list of all registers>>>>>>>>>>>>>>>

  endtask

endclass : svci_master_reg_seq