How to create random dynamic 2D arrays in SystemVerilog?

SystemVerilog
,
7

In reply to Shubhabrata:

This is working as well even one 1D array.

class packet;
    rand int unsigned len;
    rand int  data[];

    constraint size_con {
        len < 2000;
        data.size == len;
    }
endclass: packet

module test;

initial begin
  packet pkt;
  pkt = new();
  pkt.randomize();
  foreach(pkt.data[i]) begin
    $display("len:%0d, data[%0d]=%0d",i, i, pkt.data[i]);
  end
end

endmodule

But how do I constraint the data of inside array?

len:877, data[877]=-90
len:878, data[878]=98
len:879, data[879]=122
len:880, data[880]=42
len:881, data[881]=-19