How to create random dynamic 2D arrays in SystemVerilog?

SystemVerilog
,
5

In reply to UVM_LOVE:

Hi ,
You are not wrong. Height is getting randomized before width gets the value . It’s a tool dependency issue, I reckon. Because, when I ran your code on eda-playground I was not getting any type of error.
Still, I changed a few things. You can try this on your tool and let me know if it worked or not.


class frame_packet;
  rand int width;
  rand int height;
  rand int data[][];
 
  constraint size_con {
    width   inside {[8:10]};
    height  inside {[8:15]};
    data.size == width;
    foreach(data[i])
    { data[i].size == height;
     foreach(data[i][j])
     data[i][j] inside{[45:70]};}
  }
      
      constraint seq{solve width before height;}
endclass
 
module test;
 
initial begin
  frame_packet pkt;
  pkt = new();
  assert(pkt.randomize());
  foreach(pkt.data[i,j]) begin
    $display("data[%0d][%0d]=%0d",i, j, pkt.data[i][j]);
  end
end
 
endmodule