How to constraint a variable in extended class based on a variable in base class?

SystemVerilog
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3

In reply to dave_59:

Hi Dave , sorry about the tags. I will add them from next time.

I understand that i have randomized only one object. So when does the randomized value of kind be used to constrain the value of vlan? because even if i do the following , the initialized value of vlan which is zero is printing.

class macframe;
    typedef enum {II,IEEE} kind_e;
    randc kind_e kind;
 
    function display();
      $display("the kind is %p",kind);
    endfunction
  endclass
 
  class bvlan extends macframe;
    bit vlan=0;
    constraint myconstraint{
      if(super.kind == "II") vlan == 1;}
 
      function display();
        super.display();
        $write("%d",vlan);
      endfunction             
  endclass
 
module tb;
macframe mac;
bvlan vlanobj;  
  initial begin
    mac = new();
    vlanobj = new();
    repeat(10)
      begin
         mac.randomize();
        vlanobj.randomize();
         mac.display();
         vlanobj.display();
      end
   end
endmodule