How to constrain the 2nd dimension of a 2D array in systemverilog

SystemVerilog
10

In reply to dave_59:

class A ;
  rand bit[1:0] mem[2][16];
  constraint C1{
                // all cases kept in single constraint
                foreach(mem[i,j]) mem[i][j] inside {0,1};
                foreach(mem[i]) mem[i].sum() with (int'(item)) <= 2 ;
                foreach(mem[,j]) mem.sum() with (int'(mem[item.index][j])) != 2 ;
               }
 
endclass
 
module t();
  A a_h = new();
  initial repeat(1) begin
      a_h.randomize();
    foreach(a_h.mem[i,])
      $display("%p", a_h.mem[i]); 
   end 
endmodule

if i ran the simulation , did see 1’s in same column… can you help here to understand this?
Compiler version S-2021.09; Runtime version S-2021.09; May 22 09:22 2023
'{'h0, 'h0, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h0}
'{'h0, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h0, 'h0, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h0}
link : Edit code - EDA Playground
Thanks in advance