In reply to chr_sue:
Hi Christoph,
I am sorry that I do not understand what you mean by using macros. Could you please describe the solution in details?
In the connect phase of the agent, I have assigned the value to flash1_vif by uvm_config_db#()::get… (flash1_vif is connected to the verilog flash model). It seems that this the reason that the connection from dut_flash_vif to flash1_vif ( this.flash1_vif = this.dut_flash_vif;) does not work. In the vcs simulation, I can see the value of flash1_vif is top.flash1_if. Is this idea to assign dut.flash1_if to flash1_vif by uvm_config_db and then connect dut_flash_vif to flash1_vif feasible?
Some flash interface signals are bidirectional. If we use a driver to drive signals from dut_flash_vif to flash1_vif, we need to the refer to the output enable signal inside the DUT to control who should drive the bidirectional signals. Referring to the directional control signal is not a good idea. Is there any better idea to solve this problem?
Thanks.
Christine