In reply to cgales:
thank you, cgales, for your answer. I downloaded that file, but “readme” is very much alike.
I tried to use tips from that “readme” file (except for the line “You must then obtain from your SystemVerilog tool vendor a tool-specific distribution overlay”, for i don’t understand, what is “distribution overlay”). I made a new progect “hello_world”, and added “uvm.sv” in that project. i also wrote in file properties “+incdir+ $UVM_HOME/src” (i’ve created $UVM_HOME environment variable before doing it). Still, “uvm.sv” cannot be compiled. errors appear, because compilator refers “to ovm-2.1.1” folder (located in qustasim root directory) for some files and these files cannot be compiled (for some reason). what am i doing wrong? Why does compilator, while compiling top uvm file (uvm.sv), refers to some ovm files, which i haven’t dowloded from accellera site?