How to connect interface to internal signals of a module?

SystemVerilog
5

In reply to dave_59:

Dave, you said that the interface signals would have to be declared as ports. Would a modport work instead?

interface dut_internal_if;
  logic a;
  logic b;

  modport dut_mp (
    input  a,
    input  b
  );
endinterface: dut_internal_if

bind dut:dut_iii dut_internal_if.dut_mp if_iii (.a(a),.b(b));