How to connect interface to internal signals of a module?

SystemVerilog
2

You use the bind construct and make the interface signals ports instead of internal to the interface.

interface dut_internal_if(
input  logic X,
  logic Y
);
endinterface: dut_internal_if

module test;

dut dut_iii(...);

bind dut:dut_iii dut_internal_if if_iii (.X(a),.Y(b));

endmodule

See my DVCon paper for a complete example.