In reply to chr_sue:
there are 10 transaction in write _sequence _item:
class ram_write_10_addr_seq extends write_base_sequence;
`uvm_object_utils(ram_write_10_addr_seq)
function new(string name="ram_write_10_addr_seq");
super.new(name);
endfunction
task body();
for(int i=0;i<10;i++) begin
req=write_txn::type_id::create("req");
start_item(req);
assert(req.randomize()with{addr_0==i[7:0]; addr_1 == i[7:0]+10;csn_0==0;csn_1==0;wen_0==1;wen_1==1;})
finish_item(req);
end
endtask
endclass
there are 10 read transaction in read_sequence_item:
class ram_read_10_addr_seq extends read_base_sequence;
`uvm_object_utils(ram_read_10_addr_seq)
function new(string name="ram_read_10_addr_seq");
super.new(name);
endfunction
task body();
for(int i=0;i<10;i++) begin
req=read_txn::type_id::create("req");
start_item(req);
assert(req.randomize()with{addr_1==i[7:0]; addr_0 == i[7:0]+10;csn_0==0;csn_1==0;ren_0==1;ren_1==1;})
finish_item(req);
end
endtask
endclass