How to combine req and rsp sequence item into single class?

UVM
, ,
3

In reply to chr_sue:

In reply to UVM_SV_101:
Please show the code of your req and rsp.


//sequence_item_class
class ram_seq_item extends uvm_sequence_item;

   `uvm_object_utils(ram_seq_item)

   function new(string name="ram_seq_item");
      super.new(name);
   endfunction

   rand bit valid;
  rand bit [7:0] addr;
  rand bit [31:0] data_in;
  rand bit cmd;
  rand bit ready;
  rand bit out_valid;
  rand bit [31:0] data_out;
  rand bit [31:0]  tran_id;


endclass

//scoreboard
`uvm_analysis_imp_decl(_in)
`uvm_analysis_imp_decl(_out)

class ram_scoreboard extends uvm_scoreboard;

   `uvm_component_utils(ram_scoreboard)

    uvm_analysis_imp_in   #(ram_seq_item, ram_scoreboard) sb_ap_in; //driven thru monitor
    uvm_analysis_imp_out  #(ram_seq_item, ram_scoreboard) sb_ap_out;
  
    ram_seq_item ram_req[int];
    ram_seq_item ram_rsp[int];

    //need to combine req and rsp and send through analysis port
    

    //new constructor
    //code here

    function void write_in(ram_seq_item trans);
     ram_req[trans.addr] = trans;
   endfunction
   
   function void write_out(ram_seq_item trans);
     ram_rsp[trans.addr] = trans;
   endfunction

endclass