Hello: I need to know how to check the connectivity of two signals using system verilog assertions. Here I have property called p_connect_check, property p_connect_check (en, tb_sig, dut_sig); @(posedge clk) disable iff(en) (tb_sig == dut_sig) ; endproperty : p_connect_ch…

dave_59 September 23, 2021, 6:23pm 3

In reply to @VlsiYJ:

There’s no awvalid in your assertions.

Usually there are better approaches to validate connectivity:

How to check the connectivity of tb and dut signals using SVA?